1. Field of the Invention
The present invention relates to a flat display screen comprising a microtip cathode for electronically bombarding an anode including phosphor elements.
The present invention relates to flat display screens, and more particularly to so-called cathodoluminescent screens, whose anode supports phosphors separated one from the other by insulating strips which can be excited by electronic bombardment. The electronic bombardment requires the phosphors to be biased and can be generated by microtips, low extraction potential layers or thermo-ionic sources. The invention more particularly applies to the switching of the anode of a flat display screen.
To simplify, the following description only deals with color microtip screens, but the invention generally applies to the various above-mentioned screens and analog.
2. Discussion of the Related Art
FIG. 1 represents the functional structure of a flat microtip screen.
Such a microtip screen is mainly formed by a cathode 1 including microtips 2 and a gate 3 with holes 4 corresponding to the positions of microtips 2. Cathode 1 is disposed so as to face a cathodoluminescent anode 5, formed on a glass substrate 6 that constitutes the screen surface.
The operation and an exemplary structure of such a microtip screen are described in U.S. Pat. No. 4,940,916 assigned to Commissariat a l'Energie Atomique.
Cathode 1 is arranged in columns and is constituted, onto a glass substrate 10, of cathode conductors arranged in meshes from a conductive layer. The microtips 2 are disposed onto a resistive layer 11 that is deposited onto the cathode conductors and are disposed inside the meshes defined by the cathode conductors. FIG. 1 partially represents the inside of a mesh, without the cathode conductors. Cathode 1 is associated with gate 3 which is arranged in rows. An insulating layer (not shown) is interposed between the cathode conductors and gate 3. The intersection of a row of gate 3 with a column of cathode 1 defines a pixel.
This device uses the electric field generated between cathode 1 and gate 3 so that electrons are transferred from microtips 2 toward phosphors 7 of anode 5. In color screens, the anode 5 is provided with alternate phosphor strips 7, each corresponding to a color (red, green, blue). The strips are separated one from the other by an insulating material 8. The phosphors 7 are deposited onto electrodes 9, which are constituted by corresponding strips of a transparent conductive layer such as indium and tin oxide (ITO). The groups of red, green and blue strips are alternatively biased with respect to cathode 1 so that the electrons extracted from the microtips 2 of one pixel of the cathode/gate are alternatively directed toward the facing phosphors 7 of each color.
Generally, the rows of gate 3 are sequentially biased at a voltage of approximately 80 volts whereas the phosphor strips (for example 7g in FIG. 1) that must be excited are biased at a voltage of approximately 400 volts, the other strips (for example 7r and 7b in FIG. 1) are at a zero voltage. The columns of cathode 1, whose potential determines for each row of gate 3 the brightness of the pixel defined by the intersection of the cathode column and the gate row in the considered color, are brought to respective voltages ranging between a maximum emission potential and a zero-emission potential (for example 0 and 30 volts, respectively).
The values of the biasing voltages are determined by the characteristics of the phosphors 7 and microtips 2. Conventionally, below a voltage difference of 50 volts between the cathode and the gate, no electron emission occurs, and the maximum emission used corresponds to a voltage difference of 80 volts.
FIG. 2 represents an exemplary conventional biasing or switching device, of a group of conductive strips 9 supporting phosphors. Such a device is integrated in a control circuit (not shown) of the screen. For color screens, the control circuit includes three of these devices (one for each color).
A conventional switching device includes two MOS power transistors MP and MN, having a P-channel and an N-channel, respectively. The source of transistor MP is connected to a positive addressing voltage V.sub.Ah (for example approximately 400 volts), whereas its drain is connected to the drain of transistor MN, whose source is connected to a zero voltage (ground M). The drains of transistors MP and MN are connected to a first terminal of a resistor R.sub.1, whose other terminal forms an output terminal 20 of the device. Terminal 20 is connected to the related group of phosphor supporting strips.
The gates of transistors MP and MN receive control signals C.sub.P and C.sub.N, respectively, which are delayed over time to switch the device output 20 between voltage V.sub.Ah and ground. The control signals C.sub.P and C.sub.N are two-state signals. Signals C.sub.P and C.sub.N are at a low state during the frame time of the color with which the device is associated and at a high state during the frame times of the other two colors. The high and low states of the control signals C.sub.P and C.sub.N are, for example, 0 and 5 volts, respectively.
Signals C.sub.P and C.sub.N are provided to control terminals 21 and 22, respectively. The gate of transistor MP is connected to terminal 21, through a resistor R.sub.3 connected in series with a capacitor C.sub.1. The gate of transistor MN is connected to terminal 22 through a resistor R.sub.4. The gate of transistor MP is also connected to voltage V.sub.Ah through a Zener diode D.sub.Z1 and a resistor R.sub.2 which are parallel connected.
The device output 20 is switched between voltage V.sub.Ah and ground on the edges of the control signals C.sub.P and C.sub.N. Capacitor C.sub.1 is designed to enable switching of transistor MP from the control signal C.sub.P, whose potentials are referenced to ground and not to voltage V.sub.Ah.
To turn on transistor MP, the voltage of its gate should be set to a value lower than voltage V.sub.Ah. Assuming that transistor MP is off, a falling edge of signal C.sub.P is provided, as a pulse, by capacitor C.sub.1 to the gate of transistor MP, which is turned on. In contrast, the occurrence of the next (rising) edge of signal C.sub.P turns off transistor MP by setting its gate to a voltage equal to voltage V.sub.Ah. The Zener diode D.sub.Z1 is designed to protect transistor MP by limiting the voltage difference between its gate and its source to a value corresponding to the Zener voltage, for example 4.7 volts. The Zener diode D.sub.Z1 is also designed to prevent the gate voltage from substantially exceeding voltage V.sub.Ah.
However, for the edges of signal C.sub.P to cause the switching of transistor MP, a condition must be satisfied. The time constant, resulting from the gate capacitance of transistor MP associated with resistor R.sub.2, should be higher than the time constant resulting from the association of resistor R.sub.3 with capacitor C.sub.1, and the gate capacitance of transistor MP. In other words, the values of resistors R.sub.2 and R.sub.3 and capacitor C.sub.1 are selected so that R.sub.2 C.sub.g &gt;R.sub.3 (C.sub.1 +C.sub.g), where C.sub.g is the gate capacitance of transistor MP.
Transistor MN is controlled by signal C.sub.N. Since transistor MN is an N-channel transistor and its source is connected to ground, signal C.sub.N can be applied to its gate without using a capacitor. When signal C.sub.N is in a high state (for example 5 volts), transistor MN is on because its gate voltage is higher than its source voltage. In contrast, when signal C.sub.N is grounded, transistor MN is off.
A drawback of conventional color screens is that, when one group of strips of a predetermined color is biased, a spurious emission of the other two colors occurs.
This phenomenon is illustrated in FIG. 3 which is a schematic cross-sectional view along a row of gate 3 of a screen pixel. For the sake of clarity, only a few microtips 2 are represented in FIG. 3 whereas there are in practice several thousand microtips per screen pixel.
In the case of a green frame, the conductive strips 9 supporting the green phosphors 7g are addressed and biased at a positive voltage, for example 400 volts, whereas the conductive strips 9r and 9b respectively supporting the red 7r and blue 7b phosphors are in a quiescent state, at a zero voltage.
When the microtips 2 of a predetermined pixel emit electrons, some spurious electrons are not attracted by the green phosphor strips 7g but by the red 7r or blue 7b phosphor strips of this pixel, or even of adjacent pixels facing the rows of gate 3. This spurious bombardment is sometimes caused by a remaining charge of the red and blue phosphor strips even though the corresponding conductive strips 9r and 9b are at a zero voltage. Spurious capacitances are present between the phosphor strips and the supporting conductive strips. So, even when the conductive strip is connected to ground, some phosphor strips may remain biased at a voltage higher than the minimum biasing voltage (0 volt) of the microtips because of these spurious capacitances and of the high addressing voltage (approximately 400 volts). The spurious bombardment can be increased by a ballistic effect, which causes that some electrons emitted by the microtips facing the red or blue strips have not enough time to be deviated and attracted by the green phosphor strips. In FIG. 3, the electron path is symbolically represented by arrows, the path of the spurious electrons being represented by dotted lines.